A Survey of Research and Practices in Multiprocessor System on Chip Design Space Exploration

This survey presents a perspective on the existing research and practices initiated for the Design Space Exploration (DSE) in Multiprocessor System on Chip (MPSoC) technology. Reduction in size as well as adding more functionality within a single chip by incorporating multiple processors remains the key in the development of the modern MPSoC. This rapid development has been made possible because of the techniques used for scaling down the size of the chip in the field of integrated circuits. MPSoC has been considered as the best candidate for applications such as networking, telecommunication, multimedia, etc. which require high computational demand, high performance, flexibility, high energy efficiency, and low cost design. The designers have the onerous task of building MPSoCs for such applications because they have huge design options in terms of Processing Elements (PEs), micro-architectural features, interconnects, etc. to be considered with specific constraints. Exhaustive search is prohibitive because of the sheer design space size as well as the time to market considerations. Coverage of design space during the exploration process, and evaluating a single design point for finding the optimal design are the two issues that should be considered in any DSE process. This paper provides a comprehensive survey on the existing DSE techniques at the system and micro-architectural levels, the evaluation methodologies and the tools/frameworks with their comparison with respect to the design parameters considered.